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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tlv755p sbvs320a ? november 2017 ? revised may 2018 tlv755p 500-ma, low i q , small size, low dropout regulator 1 1 features 1 ? input voltage range: 1.45 v to 5.5 v ? low i q : 25 a (typical) ? low dropout: ? 238 mv (maximum) at 500 ma (3.3 v out ) ? output accuracy: 1% (maximum at 85 c) ? built-in soft-start with monotonic v out rise ? foldback current limit ? active output discharge ? high psrr: 46 db at 100 khz ? stable with a 1- f ceramic output capacitor ? packages: ? 2.9-mm 1.6-mm sot-23-5 ? 1-mm x 1-mm x2son-4 ? 2 mm 2 mm wson-6 2 applications ? set-top boxes, tv, and gaming consoles ? portable and battery-powered equipment ? desktop, notebooks, and ultrabooks ? tablets and remote controls ? white goods and appliances ? grid infrastructure and protection relays ? camera modules and image sensors 3 description the tlv755p is an ultra-small, low quiescent current, low-dropout regulator (ldo) that sources 500 ma with good line and load transient performance. the tlv755p is optimized for a wide variety of applications by supporting an input voltage range from 1.45 v to 5.5 v. to minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 v to 5 v to support the lower core voltages of modern microcontrollers (mcus). additionally, the tlv755p has a low i q with enable functionality to minimize standby power. this device features an internal soft-start to lower inrush current, thus providing a controlled voltage to the load and minimizing the input voltage drop during start up. when shutdown, the device actively pulls down the output to quickly discharge the outputs and ensure a known start-up state. the tlv755p is stable with small ceramic output capacitors allowing for a small overall solution size. a precision band-gap and error amplifier provides a typical accuracy of 1%. all device versions have integrated thermal shutdown, current limit, and undervoltage lockout (uvlo). the tlv755p has an internal foldback current limit that helps reduce the thermal dissipation during short-circuit events. device information (1) part number package body size (nom) tlv755p x2son (4) 1.00 mm 1.00 mm sot-23 (5) 2.90 mm 1.60 mm son (6) 2.00 mm 2.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application startup waveform tlv755p in en out gnd c out c in on off time (ms) voltage (v) output current (ma) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0 1 25 2 50 3 75 4 100 5 125 6 150 7 175 v out v in v en i out tools & software technical documents ordernow productfolder support &community
2 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information ................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 7 7 detailed description ............................................ 12 7.1 overview ................................................................. 12 7.2 functional block diagram ....................................... 12 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 14 8 application and implementation ........................ 15 8.1 application information ............................................ 15 8.2 typical application ................................................. 19 9 power supply recommendations ...................... 20 10 layout ................................................................... 21 10.1 layout guidelines ................................................. 21 10.2 layout examples ................................................... 21 11 device and documentation support ................. 22 11.1 device support ...................................................... 22 11.2 receiving notification of documentation updates 22 11.3 community resources .......................................... 22 11.4 trademarks ........................................................... 22 11.5 electrostatic discharge caution ............................ 22 11.6 glossary ................................................................ 22 12 mechanical, packaging, and orderable information ........................................................... 22 4 revision history changes from original (november 2017) to revision a page ? released to production .......................................................................................................................................................... 1
3 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 5 pin configuration and functions dqn package 4-pin x2son top view dbv package 5-pin sot-23 top view drv package 6-pin wson with exposed thermal pad top view nc = no internal connection. (1) the nominal input and output capacitance must be greater than 0.47 f; throughout this document the nominal derating on these capacitors is 50%. make sure that the effective capacitance at the pin is greater than 0.47 f. pin functions pin i/o description name dqn dbv drv en 3 3 4 i enable pin. drive en greater than v hi to turn on the regulator. drive en less than v lo to place the ldo into shutdown mode. gnd 2 2 3 ? ground pin. in 4 1 6 i input pin. a capacitor with a value of 1 f or larger is required from this pin to ground (1) . see the input and output capacitor selection section for more information. nc ? 4 2, 5 ? no internal connection. out 1 5 1 o regulated output voltage pin. a capacitor with a value of 1 f or larger is required from this pin to ground (1) . see the input and output capacitor selection section for more information. thermal pad pad ? pad ? connect the thermal pad to a large-area ground plane. the thermal pad is internally connected to gnd. 1 out 6 in 2 nc 5 nc 3 gnd 4 en not to scale thermal pad 1 out 2 gnd 5 3 en 4 in not to scale 1 in 2 gnd 3 en 4 nc 5 out not to scale
4 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the absolute maximum rating is v in + 0.3 v or 6.0 v, whichever is smaller 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage, v in -0.3 6.0 v enable voltage, v en -0.3 6.0 v output voltage, v out -0.3 v in + 0.3 (2) v operating junction temperature range, t j -40 150 c storage temperature, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. manufacturing with less than 500-v hbm is possible with the necessary precautions. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. manufacturing with less than 250-v cdm is possible with the necessary precautions. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v in input voltage 1.45 5.5 v v out output voltage 0.6 5.0 v v en enable voltage 0 5.5 v i out output current 0 500 ma c in input capacitor 1 f c out output capacitor 1 200 f f en enable toggle frequency 10 khz t j junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tlv755 unit dqn (x2son) dbv (sot-23- 5) drv (son) 4 pins 5 pins 6 pins r ja junction-to-ambient thermal resistance 168.4 231.1 100.2 c/w r jc(top) junction-to-case (top) thermal resistance 139.1 118.4 108.5 c/w r jb junction-to-board thermal resistance 101.4 64.4 64.3 c/w jt junction-to-top characterization parameter 5.6 28.4 10.4 c/w jb junction-to-board characterization parameter 101.7 63.8 64.8 c/w r jc(bot) junction-to-case (bottom) thermal resistance 88.4 n/a 34.7 c/w
5 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.5 electrical characteristics at operating temperature range (t j = ? 40 c to 125 c), v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f, unless otherwise noted. all typical values at t j = 25 c. parameter test conditions min typ max unit v in input voltage 1.45 5.5 v v out output voltage 0.6 5.0 v output accuracy -40 c t j +85 c, dbv and drv package -1% 1% v out 1.0 v, dqn package -1.2% 1.2% -40 c t j +85 c; 0.6 v v out < 1.0 v -10 10 mv v out 1 v -1.5% 1.5% 0.6 v v out < 1 v -15 15 mv ( vout) vin line regulation v out + 0.5 v v in 5.5 v, v out > 1.5 v 2 mv vout/ iout load regulation 0.1 ma i out 500 ma dqn package 0.036 v/a dbv package 0.060 drv package 0.044 i gnd ground current t j = 25 c, i out = 0 ma 14 25 31 a -40 c t j +85 c, i out = 0 ma 33 -40 c t j +125 c, i out = 0 ma 40 i shdn shutdown current v en 0.4 v, 1.4 v v in 5.5 v, -40 c t j +125 c 0.1 1 a i cl output current limit v in = v out + v do(max) + 0.25 v v out = v out - 0.2 v, v out 1.5v 560 720 865 ma v out = 0.9 x v out, 1.5v < v out 4.5v 560 720 865 i sc short circuit current limit v out = 0 v 355 ma v do dropout voltage i out = 500ma, -40 c t j +85 c 0.6 v v out < 0.8 v 675 1080 mv 0.8 v v out < 1.0v 600 930 1.0 v v out < 1.2 v 550 780 1.2 v v out < 1.5 v 500 630 1.5 v v out < 1.8 v 350 400 1.8 v v out < 2.5 v 325 380 2.5 v v out < 3.3 v 250 300 3.3 v v out < 5.0 v 150 215 i out = 500ma, -40 c t j +125 c 0.6 v v out < 0.8 v 1140 0.8 v v out < 1.0 v 985 1.0 v v out < 1.2 v 825 1.2 v v out < 1.5 v 665 1.5 v v out < 1.8 v 425 1.8 v v out < 2.5 v 400 2.5 v v out < 3.3 v 325 3.3 v v out < 5.0 v 238 psrr power-supply rejection ratio f = 1 khz, v in = v out + 1 v, i out = 50 ma 52 db f = 100 khz, v in = v out + 1 v, i out = 50 ma 46 f = 1 mhz, v in = v out + 1 v, i out = 50 ma 52 v n output noise voltage bw = 10 hz to 100 khz; v out = 1.2 v, i out = 500 ma 71.5 v rms v uvlo undervoltage lockout v in rising 1.21 1.3 1.44 v v uvlo,hy st undervoltage lockout hysteresis v in falling 40 mv t str startup time 550 s v hi en pin high voltage (enabled) 1 v
6 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics (continued) at operating temperature range (t j = ? 40 c to 125 c), v in = v out(nom) + 0.5 v or 2.0 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f, unless otherwise noted. all typical values at t j = 25 c. parameter test conditions min typ max unit v lo en pin low voltage (enabled) 0.3 v i en enable pin current en = 5.5v 10 na t sd thermal shutdown shutdown, temperature increasing 165 c reset, temperature decreasing 155 r pulldo wn pulldown resistance v in = 5.5v 120
7 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.6 typical characteristics at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 1.45 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f (unless otherwise noted) v in = 4.3 v, v out = 3.3 v, c out = 1 f figure 1. psrr vs frequency and i out v out = 3.3 v, c out = 1 f, i out = 500 ma figure 2. psrr vs frequency and v in v in = 4.3 v, v out = 3.3 v, i out = 500 ma figure 3. psrr vs frequency and c out v out = 3.3 v, v rms bw = 10 hz to 100 khz figure 4. output spectral noise density vs frequency and c out v out = 3.3 v, i out = 500 ma, c out = 1 f, v rms bw = 10 hz to 100 khz figure 5. output spectral noise density vs frequency and i out i out = 500 ma, c out = 1 f, v rms bw = 10 hz to 100 khz figure 6. output noise voltage vs v out frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m i out = 10 ma i out = 50 ma i out = 100 ma i out = 500 ma frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m v in 3.8 v 4 v 4.3 v 4.5 v 5 v frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m c out = 1 p f c out = 10 p f c out = 22 p f c out = 100 p f frequency (hz) noise ( p v/ ? hz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10 100 1k 10k 100k 1m 10m c out 1 p f, 143 p v rms 10 p f, 150 p v rms 22 p f, 149 p v rms 100 p f, 146 p v rms frequency (hz) noise ( p v/ ? hz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10 100 1k 10k 100k 1m 10m i out 10 ma, 140 p v rms 50 ma, 142 p v rms 100 ma, 142 p v rms 500 ma, 143 p v rms output voltage (v) output noise voltage ( p v rms ) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 40 60 80 100 120 140 160 180 200 220
8 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 1.45 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f (unless otherwise noted) v out = 3.3 v, c out = 1 f, v in slew rate = 1 v/ s figure 7. line transient v in = 5 v, v out = 3.3 v, c out = 1 f, i out slew rate = 1 a/ s figure 8. 3.3-v, 1-ma to 500-ma load transient figure 9. v in = v en power-up figure 10. v in = v en shutdown v in = 5 v, i out = 100 ma, v en slew rate = 1 v/ s, v out = 3.3 v figure 11. en startup figure 12. load regulation vs i out time (ms) voltage (v) output current (ma) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0 1 25 2 50 3 75 4 100 5 125 6 150 7 175 v out v in v en i out time (ps) output voltage (v) output current (a) 0 40 80 120 160 200 240 280 320 360 400 440 480 3.2 0 3.225 80 3.25 160 3.275 240 3.3 320 3.325 400 3.35 480 3.375 560 3.4 640 v out i out time (ms) input voltage (v) output voltage (v) 0 20 40 50 0 3.28 1 3.288 2 3.296 3 3.304 4 3.312 5 3.32 6 3.328 v in v out time (ms) voltage (v) 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 v in v out time (ms) voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 v in v out output current (ma) output voltage (mv) 0 50 100 150 200 250 300 350 400 450 500 -30 -25 -20 -15 -10 -5 0 5 10 -40c 0c 25c 85c 125c
9 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 1.45 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f (unless otherwise noted) figure 13. 3.3-v dropout voltage vs i out figure 14. 5.0-v dropout voltage vs i out v out = 3.3 v, i out = 1 ma figure 15. 3.3-v regulation vs v in (line regulation) i out = 1 ma, v out = 5 v figure 16. 5.0-v accuracy vs v in (line regulation) figure 17. i gnd vs i out v out = 3.3 v, i out = 1 ma figure 18. i gnd vs v in output current (ma) dropout voltage (mv) 0 50 100 150 200 250 300 350 400 450 500 0 40 80 120 160 200 -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) gnd pin current ( p a) 0 1 2 3 4 5 6 0 50 100 150 200 250 300 350 400 450 500 550 600 650 -40 q c 0 q c 25 q c 85 q c 125 q c output current (ma) 0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500 600 700 800 -40c 0c 25c 85c 125c gnd pin current (?a) input voltage (v) accuracy (%) 5 5.1 5.2 5.3 5.4 5.5 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) accuracy (%) 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -40 q c 0 q c 25 q c 85 q c 125 q c output current (ma) dropout voltage (mv) 0 50 100 150 200 250 300 350 400 450 500 0 25 50 75 100 125 150 175 200 -40 q c 0 q c 25 q c 85 q c 125 q c
10 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 1.45 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f (unless otherwise noted) v out = 3.3 v, i out = 0 ma figure 19. i q vs v in v en = 0 v figure 20. i shdn vs v in v en = 0 v figure 21. i shdn vs temperature figure 22. enable threshold vs temperature v en = 5.5 v figure 23. i en vs v in figure 24. uvlo threshold vs temperature input voltage (v) enable current ( p a) 0 1 2 3 4 5 6 0 50 100 150 200 250 -40 q c 0 q c 25 q c 85 q c 125 q c temperature ( q c) uvlo threshold (v) -50 -25 0 25 50 75 100 125 1.2 1.24 1.28 1.32 1.36 1.4 uvlo negative uvlo positive temperature ( q c) shutdown current (na) -40 -20 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160 180 temperature ( q c) enable threshold (mv) -50 -25 0 25 50 75 100 125 500 550 600 650 700 750 800 en negative en positive input voltage (v) shutdown current (na) 0 1 2 3 4 5 6 0 50 100 150 200 250 300 350 -40 q c 0 q c 25 q c 85 q c 125 q c input voltage (v) quiescent current ( p a) 0 1 2 3 4 5 6 0 50 100 150 200 250 300 -40 q c 0 q c 25 q c 85 q c 125 q c
11 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics (continued) at operating temperature t j = 25 c, v in = v out(nom) + 0.5 v or 1.45 v (whichever is greater), i out = 1 ma, v en = v in , and c in = c out = 1 f (unless otherwise noted) figure 25. v out vs i out pulldown resistor figure 26. 3.3-v foldback current limit, v out vs i out output current (ma) output voltage (mv) 0 1 2 3 4 5 0 50 100 150 200 250 300 350 400 450 500 550 600 -40 q c 0 q c 25 q c 85 q c 125 q c 0 100 200 300 400 500 600 700 800 0 0.5 1 1.5 2 2.5 3 3.5 -40c 0c 25c 85c 125c output voltage (mv) output current (ma)
12 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the tlv755p belongs to a family of next-generation, low-dropout regulators (ldos). this device consumes low quiescent current and delivers excellent line and load transient performance. the tlv755p is optimized for a wide variety of applications by supporting an input voltage range from 1.45 v to 5.5 v. to minimize cost and solution size, the device is offered in fixed output voltages ranging from 0.6 v to 5 v to support the lower core voltages of modern microcontrollers (mcus). this regulator offers foldback current limit, shutdown, and thermal protection. the operating junction temperature is ? 40 c to +125 c. 7.2 functional block diagram note: r 2 = 550 k , r 1 = adjustable. 7.3 feature description 7.3.1 undervoltage lockout (uvlo) an undervoltage lockout (uvlo) circuit disables the output until the input voltage is greater than the rising uvlo voltage (v uvlo ). this circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. when v in is less than v uvlo , the output is connected to ground with a 120- pulldown resistor. 7.3.2 enable (en) the enable pin (en) is active high. enable the device by forcing the en pin to exceed v hi . turn off the device by forcing the en pin below v lo . if shutdown capability is not required, connect en to in. the device has an internal pulldown that connects a 120- resistor to ground when the device is disabled. the discharge time after disabling depends on the output capacitance (c out ) and the load resistance (r l ) in parallel with the 120- pulldown resistor. equation 1 calculates the time constant : (1) + bandgap thermal shutdown uvlo logic current limit 120 ? in en gnd out r 1 r 2 t = 120 r l 120 + r l c out
13 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated feature description (continued) the en pin is independent of the input pin (in), but if the en pin is driven to a higher voltage than v in , the current into the en pin increases. this effect is illustrated in figure 23 . when the en voltage is higher than the input voltage there is an increased current flow into the en pin. if this increased flow causes problems in the application, sequence the en pin after v in is high, or to tie en to v in to prevent this flow increase from happening. if en is driven to a higher voltage than v in , limit the frequency on en to below 10 khz. 7.3.3 internal foldback current limit the tlv755p has an internal current limit that protects the regulator during fault conditions. the current limit is a hybrid scheme with brick wall until the output voltage is less than 0.4 v v out(nom). when the voltage drops below 0.4 v v out(nom) , a foldback current limit is implemented that scales back the current as the output voltage approaches gnd. when the output shorts, the ldo supplies a typical current of i sc . the output voltage is not regulated when the device is in current limit. in this condition, the output voltage is the product of the regulated current and the load resistance. when the device output shorts, the pmos pass transistor dissipates power [(v in ? v out ) i sc ] until thermal shutdown is triggered and the device turns off. after the device cools down, the internal thermal shutdown circuit turns the device back on. if the fault condition continues, the device cycles between current limit and thermal shutdown. the foldback current-limit circuit limits the current that is allowed through the device to current levels lower than the minimum current limit at nominal v out current limit (i cl ) during start up. see figure 26 for typical current limit values. if the output is loaded by a constant-current load during start up, or if the output voltage is negative when the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the device may not rise to the full output voltage. for constant-current loads, disable the output load until the output has risen to the nominal voltage. excess inductance can cause the current limit to oscillate. minimize the inductance to keep the current limit from oscillating during a fault condition. 7.3.4 thermal shutdown thermal shutdown protection disables the output when the junction temperature rises to approximately 165 c. disabling the device eliminates the power dissipated by the device, allowing the device to cool. when the junction temperature cools to approximately 155 c, the output circuitry is enabled again. depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. this cycling limits regulator dissipation that protects the circuit from damage as a result of overheating. activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product of the (v in ? v out ) voltage and the load current. for reliable operation, limit junction temperature to a maximum of 125 c. to estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. the internal protection circuitry protects against overload conditions but is not intended to be activated in normal operation. continuously running the device into thermal shutdown degrades device reliability.
14 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) all table conditions must be met. (2) the device is disabled when any condition is met. 7.4 device functional modes table 1 lists a comparison between the normal, dropout, and disabled modes of operation. table 1. device functional modes comparison operating mode parameter v in en i out t j normal (1) v in > v out(nom) + v do v en > v hi i out < i cl t j < t sd dropout (1) v in < v out(nom) + v do v en > v hi ? t j < t sd disabled (2) v in < v uvlo v en < v lo ? t j > t sd 7.4.1 normal operation the device regulates to the nominal output voltage when all of the following conditions are met. ? the input voltage is greater than the nominal output voltage plus the dropout voltage (v out(nom) + v do ) ? the enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold ? the output current is less than the current limit (i out < i cl ) ? the device junction temperature is less than the thermal shutdown temperature (t j < t sd ) 7.4.2 dropout operation if the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout. in this mode, the output voltage tracks the input voltage. during this mode, the transient performance of the device degrades because the pass device is in a triode state and no longer controls the output voltage of the ldo. line or load transients in dropout can result in large output-voltage deviations. when the device is in a steady dropout state (defined as when the device is in dropout, v in < v out(nom) + v do , right after being in a normal regulation state, but not during startup), the pass-fet is driven as hard as possible when the control loop is out of balance. during the normal time required for the device to regain regulation, v in v out(nom) + v do , v out can overshoot v out(nom) during fast transients. 7.4.3 disabled the output is shut down by forcing the enable pin below v lo . when disabled, the pass device is turned off, internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from the output to ground. the active pulldown is on when sufficient input voltage is provided.
15 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 input and output capacitor selection the tlv755p requires an output capacitance of 0.47 f or larger for stability. use x5r- and x7r-type ceramic capacitors because these capacitors have minimal variation in capacitance value and equivalent series resistance (esr) over temperature. when selecting a capacitor for a specific application, consider the dc bias characteristics for the capacitor. higher output voltages cause a significant derating of the capacitor. as a general rule, ceramic capacitors must be derated by 50%. for best performance, ti recommends a maximum output capacitance value of 200 f. place a 1 f or greater capacitor on the input pin of the ldo. some input supplies have a high impedance. placing a capacitor on the input supply reduces the input impedance. the input capacitor counteracts reactive input sources and improves transient response and psrr. if the input supply has a high impedance over a large range of frequencies, several input capacitors are used in parallel to lower the impedance over frequency. use a higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several inches from the input power source. 8.1.2 dropout voltage the tlv755p uses a pmos pass transistor to achieve low dropout. when (v in ? v out ) is less than the dropout voltage (v do ), the pmos pass device is in the linear region of operation and the input-to-output resistance is the r ds(on) of the pmos pass element. v do scales linearly with the output current because the pmos device functions like a resistor in dropout mode. as with any linear regulator, psrr and transient response degrade as (v in ? v out ) approaches dropout operation. see figure 13 and figure 14 for typical dropout values. 8.1.3 exiting dropout some applications have transients that place the ldo into dropout, such as slower ramps on v in during start-up. as with other ldos, the output may overshoot on recovery from these conditions. a ramping input supply causes an ldo to overshoot on start-up when the slew rate and voltage levels are in the correct range; see figure 27 . use an enable signal to avoid this condition.
16 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) figure 27. startup into dropout line transients out of dropout can also cause overshoot on the output of the regulator. these overshoots are caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to the correct voltage for proper regulation. figure 28 illustrates what is happening internally with the gate voltage and how overshoot can be caused during operation. when the ldo is placed in dropout, the gate voltage (vgs) is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. however, if a line transient occurs while the device is in dropout, the loop is not in regulation and can cause the output to overshoot until the loop responds and the output current pulls the output voltage back down into regulation. if these transients are not acceptable, then continue to add input capacitance in the system until the transient is slow enough to reduce the overshoot. input voltage output voltage output voltage in normal regulation. dropout v out = v in - v do v in = v out(nom) + v do response time for ldo to get back into regulation. load current discharges output voltage. voltage time
17 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) figure 28. line transients from dropout 8.1.4 reverse current as with most ldos, excessive reverse current can damage this device. reverse current flows through the body diode on the pass element instead of the normal conducting channel. at high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the following conditions: ? degradation caused by electromigration ? excessive heat dissipation ? potential for a latch-up condition conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of v out > v in + 0.3 v: ? if the device has a large c out and the input supply collapses with little or no load current ? the output is biased when the input supply is not established ? the output is biased above the input supply output voltage in normal regulation dropout v out = v in - v do transient response time of the ldo load current discharges output voltage voltage time vgs voltage for normal operation vgs voltage in dropout (pass device fully on) v do gate voltage input voltage vgs voltage for normal operation input voltage output voltage vgs voltage (pass device fully off)
18 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) if reverse current flow is expected in the application, external protection must be used to protect the device. figure 29 shows one approach of protecting the device. figure 29. example circuit for reverse current protection using a schottky diode 8.1.5 power dissipation (p d ) circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (pcb), and correct sizing of the thermal plane. the pcb area around the regulator must be as free of other heat-generating devices as possible that cause added thermal stresses. as a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. use equation 2 to approximate p d : p d = (v in ? v out ) i out (2) power dissipation must be minimized to achieve greater efficiency. this minimizing process is achieved by selecting the correct system voltage rails. proper selection helps obtain the minimum input-to-output voltage differential. the low dropout of the device allows for maximum efficiency across a wide range of output voltages. the main heat-conduction path for the device is through the thermal pad on the package. as such, the thermal pad must be soldered to a copper pad area under the device. this pad area contains an array of plated vias that conduct heat to inner plane areas or to a bottom-side copper plane. the maximum allowable junction temperature (t j ) determines the maximum power dissipation for the device. according to equation 3 , power dissipation and junction temperature are most often related by the junction-to- ambient thermal resistance (r ja ) of the combined pcb, device package, and the temperature of the ambient air (t a ). t j = t a + r ja p d (3) unfortunately, this thermal resistance (r ja ) is dependent on the heat-spreading capability built into the particular pcb design, and therefore varies according to the total copper area, copper weight, and location of the planes. the r ja value is only used as a relative measure of package thermal performance. r ja is the sum of the package junction-to-case (bottom) thermal resistance (r jcbot ) plus the thermal resistance contribution by the pcb copper. device in out gnd c out c in schottky diode internal body diode
19 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) 8.1.5.1 estimating junction temperature the jedec standard recommends the use of psi ( ) thermal metrics to estimate the junction temperatures of the ldo when in-circuit on a typical pcb board application. these metrics are not thermal resistances, but offer practical and relative means of estimating junction temperatures. these psi metrics are independent of the copper-spreading area. the key thermal metrics ( jt and jb ) are used in accordance with equation 4 and are described in the table. where: ? p d is the power dissipated as shown in equation 2 ? t t is the temperature at the center-top of the device package ? t b is the pcb surface temperature measured 1 mm from the device package and centered on the package edge (4) 8.2 typical application figure 30. tlv755p typical application 8.2.1 design requirements table 2 lists the design requirements for this application. table 2. design parameters parameter design requirement input voltage 4.3 v output voltage 3.3 v input current 500 ma (maximum) output load 250-ma dc maximum ambient temperature 70 c y y y jt j t jt d : t = t + p y jb j b jb d : t = t + p dc/dc converter tlv755p in en out gnd 1 ? f 1 ? f off on load
20 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 input current during normal operation, the input current to the ldo is approximately equal to the output current of the ldo. during startup, the input current is higher as a result of the inrush current charging the output capacitor. use equation 5 to calculate the current through the input. where: ? v out (t) is the instantaneous output voltage of the turn-on ramp ? dv out (t) / dt is the slope of the v out ramp ? r load is the resistive load impedance (5) 8.2.2.2 thermal dissipation the junction temperature can be determined using the junction-to-ambient thermal resistance (r ja ) and the total power dissipation (p d ). use equation 6 to calculate the power dissipation. multiply p d by r ja as equation 7 shows and add the ambient temperature (t a ) to calculate the junction temperature (t j ). p d = (i gnd + i out ) (v in ? v out ) (6) t j = r ja p d + t a (7) calculate the maximum ambient temperature as equation 8 shows if the (t j(max) ) value does not exceed 125 c. equation 9 calculates the maximum ambient temperature with a value of 99.95 c. t a(max) = t j(max) ? r ja p d (8) t a(max) = 125 c ? 100.2 c/w (4.3 v ? 3.3 v) (0.25 a) = 99.95 c (9) 8.2.3 application curve v in = 4.3 v, v out = 3.3 v figure 31. psrr vs frequency (4.3 v to 3.3 v) 9 power supply recommendations connect a low output impedance power supply directly to the in pin of the tlv755p. if the input source is reactive, consider using multiple input capacitors in parallel with the 1- f input capacitor to lower the input supply impedance over frequency. frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m i out = 10 ma i out = 50 ma i out = 100 ma i out = 500 ma i = out(t) c out out dv (t) dt v out (t) r load +
21 tlv755p www.ti.com sbvs320a ? november 2017 ? revised may 2018 product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines ? place input and output capacitors as close as possible to the device. ? use copper planes for device connections to optimize thermal performance. ? place thermal vias around the device to distribute the heat. 10.2 layout examples figure 32. layout example for the dqn package figure 33. layout example for the dbv package figure 34. layout example for the drv package v out v in gnd plane represents via used for application specific connections 1 23 4 5 c out c in en v in v out gnd plane represents via used for application specific connections 1 23 4 6 c in c out en 5 out in gnd plane represents via used for application specific connections 12 3 4 c in c out en
22 tlv755p sbvs320a ? november 2017 ? revised may 2018 www.ti.com product folder links: tlv755p submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for the most current package and ordering information see the package option addendum at the end of this document, or visit the device product folder on www.ti.com . (2) output voltages from 0.6 v to 5 v in 50-mv increments are available. contact the factory for details and availability. 11 device and documentation support 11.1 device support 11.1.1 device nomenclature table 3. device nomenclature (1) (2) product v out tlv755 xx(x)pyyyz xx(x) is the nominal output voltage. for output voltages with a resolution of 100 mv, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 v; 125 = 1.25 v). p indicates an active output discharge feature. all members of the tlv755p family actively discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. r is for reel (3000 pieces), t is for tape (250 pieces). 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 28-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv75507pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kd tlv75507pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kd tlv75509pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1haf tlv75509pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ax tlv75509pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ax tlv75509pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1hdh tlv75510pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fpf tlv75510pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ke tlv75510pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ke tlv75510pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1guh tlv75511pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 e8 tlv75512pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fqf tlv75512pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ag tlv75512pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ag tlv75512pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1gvh tlv75515pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1frf tlv75515pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kf
package option addendum www.ti.com 28-aug-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv75515pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kf tlv75515pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1gwh tlv75518pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fsf tlv75518pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ai tlv75518pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ai tlv75518pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1gxh tlv75519pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1hbf tlv75519pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 b5 tlv75519pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 b5 tlv75519pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1heh tlv75525pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1ftf tlv75525pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 aj tlv75525pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 aj tlv75525pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1gzh tlv75528pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fuf tlv75528pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kg tlv75528pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 kg tlv75528pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1h1h
package option addendum www.ti.com 28-aug-2018 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlv75529pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1hcf tlv75529pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1hfh tlv75530pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fvf tlv75530pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ki tlv75530pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 ki TLV75530PDRVR preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1h2h tlv75533pdbvr active sot-23 dbv 5 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 1fwf tlv75533pdqnr active x2son dqn 4 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 an tlv75533pdqnt active x2son dqn 4 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 an tlv75533pdrvr preview wson drv 6 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 1h3h (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 28-aug-2018 addendum-page 4 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv75507pdqnr x2son dqn 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75507pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75507pdqnt x2son dqn 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75507pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75509pdbvr sot-23 dbv 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 q3 tlv75509pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75509pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75509pdqnr x2son dqn 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75509pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75509pdqnt x2son dqn 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75509pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75509pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75510pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75510pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75510pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75510pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75510pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75511pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 package materials information www.ti.com 31-aug-2018 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv75511pdqnr x2son dqn 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75512pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75512pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75512pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75512pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75512pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75515pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75515pdbvr sot-23 dbv 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 q3 tlv75515pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75515pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75515pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75515pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75518pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75518pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75518pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75518pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75518pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75519pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75519pdqnr x2son dqn 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75519pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75519pdqnt x2son dqn 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 q2 tlv75519pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75519pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75519pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75525pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75525pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75525pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75525pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75525pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75528pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75528pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75528pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75528pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75528pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75529pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75529pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75529pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 tlv75530pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 tlv75530pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75530pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 TLV75530PDRVR wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 TLV75530PDRVR wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75533pdbvr sot-23 dbv 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 q3 package materials information www.ti.com 31-aug-2018 pack materials-page 2
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlv75533pdqnr x2son dqn 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75533pdqnt x2son dqn 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 q2 tlv75533pdrvr wson drv 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 q2 tlv75533pdrvr wson drv 6 3000 178.0 8.4 2.25 2.25 1.0 4.0 8.0 q2 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tlv75507pdqnr x2son dqn 4 3000 183.0 183.0 20.0 tlv75507pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75507pdqnt x2son dqn 4 250 183.0 183.0 20.0 tlv75507pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75509pdbvr sot-23 dbv 5 3000 180.0 180.0 18.0 tlv75509pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75509pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75509pdqnr x2son dqn 4 3000 183.0 183.0 20.0 tlv75509pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75509pdqnt x2son dqn 4 250 183.0 183.0 20.0 tlv75509pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75509pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75510pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 package materials information www.ti.com 31-aug-2018 pack materials-page 3
device package type package drawing pins spq length (mm) width (mm) height (mm) tlv75510pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75510pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75510pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75510pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75511pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75511pdqnr x2son dqn 4 3000 183.0 183.0 20.0 tlv75512pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75512pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75512pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75512pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75512pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75515pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75515pdbvr sot-23 dbv 5 3000 180.0 180.0 18.0 tlv75515pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75515pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75515pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75515pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75518pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75518pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75518pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75518pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75518pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75519pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75519pdqnr x2son dqn 4 3000 183.0 183.0 20.0 tlv75519pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75519pdqnt x2son dqn 4 250 183.0 183.0 20.0 tlv75519pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75519pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75519pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75525pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75525pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75525pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75525pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75525pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75528pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75528pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75528pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75528pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75528pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75529pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75529pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75529pdrvr wson drv 6 3000 205.0 200.0 33.0 tlv75530pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75530pdqnr x2son dqn 4 3000 184.0 184.0 19.0 package materials information www.ti.com 31-aug-2018 pack materials-page 4
device package type package drawing pins spq length (mm) width (mm) height (mm) tlv75530pdqnt x2son dqn 4 250 184.0 184.0 19.0 TLV75530PDRVR wson drv 6 3000 205.0 200.0 33.0 TLV75530PDRVR wson drv 6 3000 210.0 185.0 35.0 tlv75533pdbvr sot-23 dbv 5 3000 210.0 185.0 35.0 tlv75533pdqnr x2son dqn 4 3000 184.0 184.0 19.0 tlv75533pdqnt x2son dqn 4 250 184.0 184.0 19.0 tlv75533pdrvr wson drv 6 3000 210.0 185.0 35.0 tlv75533pdrvr wson drv 6 3000 205.0 200.0 33.0 package materials information www.ti.com 31-aug-2018 pack materials-page 5
generic package view images above are just a representation of the package family, actual package may vary. refer to the product data sheet for package details. drv 6 wson - 0.8 mm max height plastic small outline - no lead 4206925/f
www.ti.com package outline c 6x 0.35 0.25 1.6 0.1 6x 0.3 0.2 2x 1.3 1 0.1 4x 0.65 0.8 0.7 0.05 0.00 b 2.1 1.9 a 2.1 1.9 (0.2) typ wson - 0.8 mm max height drv0006a plastic small outline - no lead 4222173/b 04/2018 pin 1 index area seating plane 0.08 c 1 3 4 6 (optional) pin 1 id 0.1 c a b 0.05 c thermal pad exposed 7 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 5.500
www.ti.com example board layout 0.07 min all around 0.07 max all around (1) 4x (0.65) (1.95) 6x (0.3) 6x (0.45) (1.6) (r0.05) typ ( 0.2) via typ (1.1) wson - 0.8 mm max height drv0006a plastic small outline - no lead 4222173/b 04/2018 symm 1 3 4 6 symm land pattern example scale:25x 7 notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if some or all are implemented, recommended via locations are shown. solder mask opening solder mask metal under solder mask defined metal solder mask opening solder mask details non solder mask defined (preferred)
www.ti.com example stencil design 6x (0.3) 6x (0.45) 4x (0.65) (0.7) (1) (1.95) (r0.05) typ (0.45) wson - 0.8 mm max height drv0006a plastic small outline - no lead 4222173/b 04/2018 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. solder paste example based on 0.125 mm thick stencil exposed pad #7 88% printed solder coverage by area under package scale:30x symm 1 3 4 6 symm metal 7

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2

package outline dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. features may not exist. recommend use of pin 1 marking on top of package for orientation purposes. 5. shape of exposed side leads may differ. 6. number and location of exposed tie bars may vary. www.ti.com b a seating plane c 0.08 pin 1 index area 0.1 c a b 0.05 c pin 1 id (optional) note 4 exposed thermal pad 1 2 3 4 1 1.05 0.95 1.05 0.95 0.4 max 2x 0.65 0.48 +0.12 -0.1 3x 0.30 0.15 0.3 0.2 4x 0.28 0.15 0.05 0.00 (0.11) note 5 note 6 note 6 5 (0.07) typ (0.05) typ
example board layout dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: (continued) 7. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271) . 8. if any vias are implemented, it is recommended that vias under paste be filled, plugged or tented. www.ti.com solder mask defined solder mask detail 0.05 min all around solder mask opening metal under solder mask land pattern example scale: 40x symm symm 1 2 3 4 4x (0.21) 4x (0.36) (0.65) (0.86) ( 0.48) see detail 4x (0.18) (0.22) typ exposed metal clearance 4x (0.03) exposed metal 5
example stencil design dqn0004a x2son - 0.4 mm max height plastic small outline - no lead 4215302/e 12/2016 notes: (continued) 9. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. www.ti.com solder paste example based on 0.075 - 0.1mm thick stencil exposed pad 88% printed solder coverage by area scale: 60x symm symm 1 2 3 4 solder mask edge 4x (0.21) 4x (0.4) (0.65) (0.9) ( 0.45) 4x (0.03) 4x (0.235) 4x (0.22) 5
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